The present disclosure relates to non-volatile memory structures, and more particularly, to techniques for forming bit lines in such structures.
Semiconductor memory has become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other electronic devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Both EEPROM and flash memory utilize a transistor structure having a floating gate that is positioned above and insulated from the channel region in a semiconductor substrate, as well as between the source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to permit conduction between its source and drain is controlled by the level of charge on the floating gate.
In one embodiment, the control gates associated with rows of memory elements are also utilized as word line connections. Bit line connections are made by forming bit lines in a metal layer above the word lines in correspondence with columns of memory elements, and forming vias through metal layer to contact the drain regions of the memory elements. The state of a non-volatile memory element can be determined by applying a pre-charge voltage to the bit line, applying a reference voltage to the control gate, then discharging the bit line and sensing the voltage on the bit line. If the memory element is on, the bit line voltage will drop. If the bit line is off, the bit line voltage will not drop, but will be about the same as during the pre-charge state.
One problem with sensing memory elements simultaneously is capacitive coupling of adjacent bit lines. The sensed bit line may be coupled down by the adjacent bit line(s) if the adjacent bit lines voltage drops. The sensed memory elements may therefore look like they are on, leading to read errors. The continuing increase in scaling of transistors leads to increases in total bit line capacitance and parasitic bit line to bit line capacitance thereby further exacerbating this problem.
One solution to the problem of capacitive coupling, or bit line to bit line crosstalk, is to avoid sensing all bit lines at once, and instead, only sense odd or even bit lines, and then to turn the bit lines off for elements already sensed. However, the time delay associated with sensing odd and even bit lines impacts memory performance. Thus, it would be desirable to reduce the capacitive coupling effects to obtain enhanced performance of sensing schemes.